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• Re: Extending IPv4 with source translation/source privacy. Another way of looking at this idea is from the point of "address
  translation" also known as NAT.
  I'm a bit rusty about NAT but as far as I remember NAT works by using public
  available resources like public ip addresses, and public ports and tries
  to attach a single public ip address and multiple public ports to multiple
• Re: Extending IPv4 with source translation/source privacy. Some furher thoughts/clearifications on this idea:
  The idea assumes that at each router a modest ammount of traffic passes it.
  So the idea assumes that the router will see less than half of the total ip
  range go past it.
  The idea would fail if 50% of the total internet ip range passes a single
  router and all ip's desire privacy option.
• Re: Renamer Port Reduction Which means that we're quite a bit beyond the point you told me you
  expected many years ago, i.e. "calculations are free, getting the data
  in & out is the only real cost".
  If you have to load the real data anyway, having a look-aside buffer
  (i.e. cache) to speed it up slightly means that you're simply doing more
• Extending IPv4 with source translation/source privacy. Hello,
  The internet protocol version 4 could be extended with source
  translation/source privacy.
  The idea is as follows:
  The ip.source is translated into something else/arbitrary along the path's
  routers to it's destination.
  Each router selects a random available ip from a table which is to replace
• New High Bandwidth Supercomputer [link]
  Maybe all you whiners out there will like this one. :-)
  The video link in the article doesn't seem to work. I'll have to see if
  I can locate it.
• Re: Renamer Port Reduction As an interesting side topic, and way off the original intent of this
  thread.....
  I have found it interesting that one can build a trace cache machine
  for a RISC design point with a 20 Gate pipestage in about 6-7 pipe
  stages, or about 8-9 pipe stages for a 16 gate pipe. However, all the
  16-gate x86 pipelines (P-Pro and derivatives, and Athlon and Opteron
• Re: Renamer Port Reduction True. You have to trade off the increased leakage due to the decreased
  space efficiency (which Mitch mentioned in another post). You leak (most)
  all the time, while clock gating often means you only pay dynamic power as
  needed...
  Ned
• Re: Renamer Port Reduction I read comments like this in discussions like this and I wonder: why
  don't we program the way that computer architects think?
  I'm sure that, to understand the real answer to a question like that,
  I'd have to go through the experience of trying to be an architect
  myself. There isn't enough time left, and I probably never had the
• Re: Renamer Port Reduction The prior discussion was conversing about whether multiple architected
  register files were good for ILP, and how the wires (and wiring
  density) between the register file and the calculation units were
  dense and difficult.
  I brought up the point that the renamer, and its ports on the path
  towards the instruction queues is, made worse by multiple register
• call for papers ( WE APOLOGIZE IF YOU RECEIVE MULTIPLE COPIES OF THIS MESSAGE )
  ============================== ===========================
  ARPN Journal of Systems and Software
  Call for Research Papers
  [link]
  ============================== ===========================
  Dear Sir/ Madam,
• Re: Where is Bulldozer's renamer? Thanks, David (or should I say, thanks RWT.com). You're allowed to toot
  your own horn, in moderation. RWT.com is one of the best tech sites.
  By the way, I encourage you to clip quotes, rather than including all of
  my very long posts.
  Q: where did you get this information about the renamer position? I did
• Re: Renamer Port Reduction Yep.
  I originally thought that you needed a trace cache to fetch more than
  one basic block per cycle.
  With BTB unrolling - trace BTBs, rather than a trace instruction cache
  - and/or the Jourdan/Seznec N-ahead BTB, you don't need that. You can
  fetch multiple discontiguous basic blocks out of a multiported (e.g.
• Re: Renamer Port Reduction Exactly.
  You can choose how complete or incomplete you want to make the
  comparator network.
  E.g. if you have 2 inputs per operand, you might compare the first input
  to all preceding outputs, but use a sparse network for the second.
  (This is, by the way, the sort of trick that is played with incomplete
• Re: Renamer Port Reduction I think if we ever see trace cache again, it will have to be justified using
  these sorts of techniques to reduce power.
  Ned
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